Data control register for output bit 1
| SEL_P | Shift register data bit select for the first half of the HSTX clock cycle |
| SEL_N | Shift register data bit select for the second half of the HSTX clock cycle |
| INV | Invert this data output (logical NOT) |
| CLK | Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. |